The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.
Semiconductor memory devices have increasingly been used in a wide variety of electronic devices. Non-volatile semiconductor memory devices are now seen in cellular phones, personal digital assistants, digital cameras, audio recorders, digital video camcorders, and USB flash drives, just to name a few. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory devices are among the most popular non-volatile semiconductor memories.
FIG. 1 illustrates a typical memory cell utilizing a floating gate 100 that is positioned above and insulated from a channel region 102 in the semiconductor substrate 104. The floating gate 100 is positioned between source 106 and drain regions 108. A control gate 110 is placed over and insulated from the floating gate 100. The threshold voltage of the transistor is controlled by the amount of charge that is retained on its floating gate 100. That is, the minimum amount of voltage that must be applied to the control gate 110 before the transistor is turned on to permit conduction between its source 106 and drain 108, and thereby forming a channel 102 on the surface portion of the semiconductor substrate 104 immediately beneath the floating gate 100, is controlled by the level of charge on the floating gate 100.
FIG. 2 illustrates a typical two-dimensional array of floating gate memory transistors, or memory cells 210, formed on a semiconductor substrate. FIG. 2 includes several strings, known as NAND strings NS, of floating gate memory transistors 210. Each transistor 210 is coupled to the next transistor 210 in the string by coupling the source of one transistor to the drain of the next to form bit lines BL1-BLn. Each NAND string NS includes a select transistor 212, 214 on either end of the string NS of memory cells. The drain side select transistor 212 connects the NAND strings NS to respective bit lines and the source side select transistor 214 connects the NAND strings NS to a common source line 216. A plurality of word lines WL1-WLn, run perpendicular to the NAND strings NS. Each word line connects to the control gate 218 of one memory cell 210 of each NAND string NS.
Before programming a flash memory device, its memory cells are typically erased and have a certain threshold voltage, such as −2 volts. Memory cells may be erased as part of a batch erase where all the memory cells existing on the memory cell array are simultaneously erased, or as part of a block erase, where a block consists of a group of NAND cells arranged in row direction and sharing a common word line. Other methods exist which are well known in the art. For a memory cell erasure, the control gates are set to ground through their word lines, while a high voltage (e.g. 20 V) is applied to control gates through the word lines in non-selected blocks. The bit lines and source lines are turned into a floating state respectively and a high voltage (e.g. 20 V) is applied to the semiconductor substrate. By doing so, electrons are discharged into the semiconductor substrate from the floating gates of the selected memory cells and the threshold voltages of the selected memory cells are shifted in the negative direction.
When programming a flash memory device, a program voltage is typically applied to the control gate of the memory cell and its bit line is grounded. Electrons from the substrate channel are injected into the floating gate through a process known as tunneling. When electrons accumulate on the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised so that the memory cell is in the programmed state. In the case of NAND type memory, the threshold voltages after data erase are normally “negative” and defined as “1.” The threshold voltages after data write are normally “positive” and defined as “0.”
When storing one bit of digital data, the range of possible threshold voltages of the memory cell is divided into two ranges which are assigned logical data “1” and “0.” In one example of a NAND type flash memory, the voltage threshold is negative after the memory cell is erased, and defined as logic “1.” The threshold voltage after a program operation is positive and defined as logic “0.”
When the threshold voltage is negative and a read is attempted, the memory cell will turn on indicating logic “1” was stored. When the threshold voltage is positive and a read operation is attempted, the memory cell will not turn on, indicating logic “0” was stored. A memory cell can also store multiple bits of digital data, such as in Multi-Level Cell Architecture devices (MLC devices). The range of possible threshold values determines the number of possible levels of data. For example, if four levels of information are stored, there will be four threshold voltage ranges assigned to the data values “11”, “10”, “01”, and “00.” In one example of a NAND type memory, the threshold voltage after an erasure is negative and defined as “11.” Positive threshold voltages may be used for the states of “10”, “01”, and “00.”
When a memory cell is programmed, all of the memory cells on the same word line also receive the program signal. Even though the bit lines on their NAND strings are set to a supply voltage Vcc (e.g. 3-5 V), and inhibited, it is still possible for another memory cell on the same word line to be inadvertently programmed. In particular, the memory cell adjacent to the memory cell selected for programming may be especially vulnerable.
FIG. 2 shows the memory cell to be programmed S on word line WL3 along with the inhibited memory cells Q on the same word line WL3. The selected bit line BL1 is set to ground and the inhibited bit lines BL2-BLn are set to Vcc. The program signal Vpgm is applied to the selected word line WL3 and is in turn applied to the control gates 218 of the memory cells 210 along the word line WL3. This places the program signal Vpgm on memory cells 210 in both selected BL1 and unselected BL2-BLn bit lines. The unintentional programming of an unselected memory cell Q on the selected word line WL3 is called “program disturb.”
There have been many attempts to limit or prevent program disturb. Conventional self boosting is a method whereby the unselected bit lines are electrically isolated and a pass voltage is applied to the unselected word lines during programming. FIG. 3 illustrates conventional self boosting. A supply voltage Vcc (e.g. 3-5 V) is applied to both the drain 302 and control gate 304 of the unselected drain side select transistors 310 to turn the drain side select transistors 212 off, and thereby electrically isolate the unselected bit lines. A pass voltage Vpass (e.g. 10 V) is applied to the unselected word lines WL1, WL2 & WL4-WLn. The unselected word lines WL1, WL2 & WL4-WLn capacitively couple to the unselected bit lines BL2-BLn, causing a voltage (such as about 6 volts), to exist in the channel of the unselected bit lines BL2-BLn, which tends to reduce program disturb. Self boosting reduces the potential difference between channels of the unselected bit lines BL2-BLn and the program signal Vpgm that is applied to the selected word line WL3. The end result is reduced voltage across the tunnel oxide and therefore reduced program disturb, especially in the memory cells Q in the unselected bit lines BL2-BLn on the selected word line WL3.
Conventional self boosting does have its disadvantages however. A NAND string is typically programmed from the source side to the drain side. When all but the last few memory cells have been programmed, if all or most of the memory cells on the NAND string NS being inhibited were programmed, then there is negative charge in the floating gates of the previously programmed cells. Because of this negative charge on the floating gates, the boosting potential doesn't get high enough and there may still be program disturb on the last few word lines. For example, when programming one particular memory cell S, if a memory cells B on the source side word line and adjacent to inhibited memory cells Q on the selected word line were already programmed, the negative charge on their floating gates will limit the boosting level of the self boosting process and possibly cause program disturb on the memory cell Q adjacent to the programmed memory cell S.
In addition, conventional self boosting also suffers from uneven channel voltage. In conventional self boosting, channel voltage is not uniformly distributed if any cell in the string is programmed. Channel voltage on the drain side, with pre-charging, is higher than the source side. That is, memory cells on the source side are vulnerable to program disturbs. In other words, there is non-uniform channel voltage: the voltage is different through the channel. The differences in channel voltage on either side of the programmed memory cell may continue to grow as more memory cells are programmed. Further, there is pattern dependent channel voltage, such that channel voltage is different from bit line to bit line due to their varying programming/erasure patterns. The channel voltage is boosted in different amounts depending on the threshold voltages of the cells. As a result, when data is written into the selected memory cell in the selected NAND string, the stress due to the programming voltage applied to all the memory cells on the word line may cause a disturbance in the previously programmed memory cells.
Local Self Boosting (“LSB”) and Erased Area Self Boosting (“EASB”) are two schemes created to help deal with the disadvantages inherent in conventional self boosting methods.
T. S. Jung et al. proposed a local self boosting (“LSB”) technique in “A 3.3V 128 Mb Multi-Level NAND Flash Memory for Mass Storage Applications,” ISSCC96, Session 2, Flash Memory, Paper TP 2.1, IEEE, pp. 32. The system reduces the program voltage stress that causes program disturb and in particular the variance of threshold voltages of memory systems utilizing the Multi-Level Cell architecture (MLC device).
In the LSB system illustrated in FIGS. 4A and 4B, the bit line BL1 of the memory cell S being programmed is at 0 volts and the bit lines BL2-BLn of memory cells Q to be inhibited are at a supply voltage (e.g. 3-5 V). A program signal Vpgm (e.g. 20 volts) is applied to the selected word line WL3. The word lines WL2, WL4 adjacent to the selected word line WL3 are at 0 volts. A pass voltage Vpass (e.g. 8-12 volts) is applied to the remaining, unselected word lines WL1, WL5-WLn.
In the LSB method, when applying a programming voltage to the selected word line WL3, in order to reduce or prevent program disturb in memory cells 210 on the other inhibited NAND strings INS, 0 volts are applied to the word lines WL2, WL4 on either side of the selected word line WL3, so that the two memory cells above A and below B the inhibited memory cell Q are “turned off.” With the adjacent memory cells “turned off,” the channel voltage of the inhibited cell Q will not be influenced by the self-boosting in the channels of the adjacent memory cells A, B. With the program signal Vpgm applied to the selected word line WL3, the channel of the inhibited memory cell Q may be locally self boosted to a voltage level that is higher than could be reached when the inhibited memory cell's channel region is influenced by the self boosting of the other memory cells in the same inhibited NAND string INS. The result is prevented or reduced incidents of program disturb.
Care must taken when selecting an appropriate pass voltage level. For the LSB method to work, the memory cells adjacent to the inhibited memory cell must be turned off regardless of the data stored. These adjacent memory cells can have arbitrary threshold voltage levels of either a positive or negative threshold voltage. To “shut off” these adjacent memory cells by means of the back-bias effect caused by the channel voltage, the pass voltage must be at a level able to sufficiently increase the lowest threshold voltage likely seen. However, the pass voltage must not be set too high. As the pass voltage increases, the variation in threshold voltage increases as well. A threshold voltage may be increased or decreased enough to change its programmed logic state. In other words, if pass voltage is too low, self boosting in the channels will be insufficient to prevent program disturb, but if pass voltage is too high, unselected word lines may be reprogrammed.
Tanaka et al. proposed an Erased Area Self-Boosting (EASB) system, U.S. Pat. No. 6,525,964, to deal with some of the disadvantages of conventional LSB.
The EASB scheme may be applied to the conventional memory cell array that uses NAND strings and word lines, wherein the word lines are attached to one memory cell from each NAND string in the row. As illustrated in FIG. 5, to program a specific memory cell S, a program signal Vpgm (e.g. 20 volts) is applied to the word line WL3 connected to the control gate of the specific memory cell S. The word line WL4 adjacent to the selected word line WL3 on the source side is set to a level below the programming signal, such as 0 volts. A pass voltage Vpass (e.g. 8-12 volts) is applied to all the remaining word lines WL1-WL2, WL4-WLn. The pass voltage Vpass is selected to be below the level of the program signal Vpgm, but above the voltage level of the signal applied to the adjacent, source side word line WL4.
EASB may result in more uniform channel voltage and is less vulnerable to leakage, but the inhibited memory cell's Q channel voltage is lower than when using the LSB scheme. However, there is less junction leakage. The boosting ratio is also higher using EASB over LSB, which results in a higher channel voltage from self boosting for a given pass voltage.
The EASB scheme is also affected by whether the source side adjacent memory cell B has been programmed or erased, as the state of the source side adjacent memory cell B will influence the channel voltage of the inhibited memory cell Q. If the adjacent source side memory cell B is programmed, there is a negative charge on its floating gate, and the threshold voltage of the memory cell B will likely be positive. Zero volts are applied to its control gate. This results in a highly reverse biased junction under the negatively charged floating gate which can result in Gate Induced Drain Leakage (GIDL). GIDL involves electrons leaking into the self boosted channel. GIDL occurs when there is a large bias in the junction and a low or negative floating gate voltage. This is the case when the source side adjacent memory cell B is already programmed and the drain junction is boosted. GIDL will cause the self boosted voltage to leak away prematurely, resulting in a programming error. If the current leakage is high enough, the self boosted voltage level in the channel will drop with an increased risk for program disturb. In addition, the closer the selected word line WL3 is to the drain side select transistor 212, the less charge there will be in the boosted junction. Thus, the voltage in the self boosted junction will drop quicker, increasing the risk for program disturb.
If the adjacent source side memory cell B is erased, then there is a positive charge on the floating gate and the threshold voltage of the transistor B will likely be negative. The memory cell B may not even turn off when 0 volts is applied to its word line. And if the memory cell B is still on, the inhibited NAND string INS is not operating in EASB mode, but rather in the previously discussed conventional LSB mode. This is most likely to happen when other memory cells on the source side word lines are already WL4-WLn are already programmed, which tends to limit source side self boosting.
Lutze et al. proposed an Erased Area Self Boosting (EASB) system with pre-charging, U.S. Pat. No. 6,975,537, to deal with some of the limitations of LSB and EASB for programming a conventional memory array.
The EASB scheme proposed by Lutze may be applied to the conventional memory cell array that uses NAND strings and word lines, wherein the word lines are attached to one memory cell from each NAND string in the row. This EASB scheme is illustrated in FIG. 6. Before the program signal Vpgm (e.g. 18-20 volts) is applied to the word line WL3 of the selected memory cell S, the channel voltage of the source side of the inhibited NAND string SNS is first increased. If the adjacent source side memory cell B has been programmed, then raising the source side channel voltage of the inhibited NAND string SNS reduces GIDL. If the adjacent source side memory cell B has been erased, then raising the source side channel voltage of the inhibited NAND string SNS helps keep the adjacent source side memory cell B from “turning on.”
The step of pre-charging the source side channel voltage of the inhibited NAND string SNS includes applying a pre-charge voltage Vpc to the adjacent source side word line WL4 and to at least one more of the other source side word lines. Application of the pre-charge voltage Vpc is commenced prior to applying a pass voltage Vpass (e.g. 10 V). The end result will be a source side channel voltage higher than from just applying the pass voltage Vpass alone.
A supply voltage, or Vcc, (e.g. 3-5 volts) is applied to the drain region and to the control gate of the drain side select transistor 212 connected to the bit line BL2-BLn containing the cell Q to be inhibited. The supply voltage Vcc is also applied to the source line 216 connected to the source side select transistor 214, but the source side select transistor control gate remains at 0 volts. The pre-charge voltage Vpc (e.g. 4 volts) is now applied to the adjacent source side word line WL4 as well as at least one other source side word line WL5. By applying the pre-charge voltage Vpc to the unselected source side word lines WL4-WL5, the source side channel voltage SNS is boosted to a voltage of Vcc-Vt, where Vt is the threshold voltage of the drain side select transistor 212. The drain side channel voltage is at Vcc-Vt. After the pre-charge phase is completed, the programming phase begins as illustrated in FIG. 7. A program signal Vpgm (e.g. 20 volts) is applied to the selected word line WL3, while a pass voltage Vpass (e.g. 8-12 V) is applied to the unselected word lines WL1-WL2 on the drain side of the selected word line WL3 (originally they were at 0 V). The pass voltage Vpass is also applied to the unselected word lines WL5-WLn on the source side except for the adjacent source side word line WL4. The drain region and control gate of the drain side select transistor 212 are both held at Vcc. Meanwhile, the word line WL4 connected to the adjacent source side memory cell B is lowered to 0 volts.
Hemink proposed a buffered bias with EASB or LSB, U.S. Pat. No. 7,161,833, attempting to improve on the LSB and EASB programming schemes. These alternative LSB and EASB schemes with buffered biasing may be applied to the conventional memory cell array that uses NAND strings and word lines, wherein the word lines are attached to one memory cell from each NAND string in the row.
The scheme according to Hemink proposed applying a biasing voltage Vpb ranging from 0 volts to some small positive voltage (e.g. 1-3 V) below the level of a pass voltage Vpass (e.g. 8-12 V) to two or more word lines (preferably adjacent) on the source side of the selected word line (for the EASB scheme). The same biasing voltage could be applied to one or more word lines (preferably adjacent) on the drain side of the selected word line as well as the source side of the selected word line (for the LSB scheme). The above described scheme should result in reduced incidents of current leakage, especially junction leakage and a reduction of programming errors and program disturb.
An embodiment of the modified EASB scheme is illustrated in FIG. 8. Two word lines WL4, WL5 (preferably adjacent) on the source side of the selected word line WL3 were grounded. The pass voltage Vpass was applied to all of the word lines WL1, WL2 on the drain side. Optionally, two or more word lines on the source side may be grounded, and may be separated from the selected word line WL3 by one or more word lines. The modified EASB scheme increases the channel length of the isolation region, helping to further reduce program disturb.
Current Leakage and particularly junction leakage may still occur between the grounded memory cells and the memory cells being programmed, and between the grounded memory cells and the memory cells to which the pass voltage has been applied. To further improve programming, rather than grounding the two word lines WL4, WL5 on the source side of the selected word line WL3, a low positive voltage Vpb may be applied instead (e.g. 1-3 V). This small voltage Vpb applied to the source side word lines WL4, WL5 suppresses current leakage while remaining adequate enough to isolate the two boosted regions in the EASB scheme.
The same buffered bias scheme may also be applied to conventional LSB. As illustrated in FIG. 9, two or more word lines (preferably adjacent) on both the source side and drain side of the selected word line WL3 are biased. Zero or low positive voltage levels Vpb (e.g. 1-3 V) are applied as desired to further reduce current leakage, program disturb, and/or altered threshold voltage levels.